Interested candidates send resume to: Google LLC, PO Box 26184 San Francisco, CA 94126 Attn: V. Cheng. Please reference job # below:
ASIC/RTL Designer (Sunnyvale, CA) Design, develop, modify, &/or test hardware needed for various Google projects. 1615.52675 Exp Inc: ASIC digital design using Verilog; synthesis, timing closure & physical design principles of digital designs; computer architecture domain knowledge; power performance analysis for ASIC designs; static timing analysis; & Perl, C++, or Python.
Electrical Engineer (Sunnyvale, CA) Design, develop, modify, &/or test hardware needed for various Google projects. 1615.50555 Exp Inc: PLCs, Digital Relays, IEC 61850 protocols, SCADA systems, historians, industrial automation & power monitoring; SKM, CAPE, ASPEN, ETAP, & CYME; AC-DC electrical drawings; compliance requirements of pertinent codes, regulations, & standards; IEEE, ANSI, NFPA & NEC Standards for successful performance of the electrical system; SOO.
Positions report to the Google SVL office & may allow for partial telecommuting.