Interested candidates send resume to: Google LLC, PO Box 26184 San Francisco, CA 94126 Attn: V. Cheng. Please reference job # below:
Hardware Design Engineer (Mountain View, CA) Design, develop, modify, &/or test hardware needed for various Google projects. #1615.54865 Exp Incl: VLSI design, hardware accelerators, & circuit design; building physical design methodologies; ASIC physical design flows; methodologies in advanced CMOS process nodes; & scripting in Perl, Tcl, & Python.
Hardware Engineer (Mountain View, CA) Design, develop, modify, &/or test hardware needed for various Google projects. #1615.54870 Exp Incl: Verilog; EDA tools; computer architecture; Sign-off tools; & ASIC physical design experience.
#1615.32502 Exp Incl: DSP tuning, validation & industry & telephony standards; audio analyzers; network technologies related to audio; audio telephony regulatory & industry standards ITU - T 3GPP & 3GPP2; speech enhancement techniques; network simulators; & audio calibration equipment.
Hardware Test Engineer (Mountain View, CA) Design, develop, modify, &/or test hardware needed for various Google projects. #1615.29288 Exp Incl: optical metrology development; operating & programming interferometers, optical profilers, spectrometers, microscopes for novel optical surface data acquisition, & analysis; optical test infrastructure & test planning development, automation & transfer or delegation; & opto-mechanical design using SolidWorks or CAD suites. Trvl Req'd.
Silicon Engineer (Mountain View, CA) Design, develop, modify, &/or test hardware needed for various Google projects. #1615.43679 Exp Incl: C, C++, Shell Scripting, Perl & Python; Verilog, Systemverilog, & SOC implementation; power delivery network design, evaluation, implementation & validation; ASIC design methodologies, chip architecture planning, & feasibility analysis; Implementation of Design for Manufacturing (DFM) & Design for Assembly (DFA) rules to improve production yields; embedded & consumer electronics hardware design; implementation of hardware system design & constraint rules; & functional ASIC design verification, design for test, & high-density interconnect design.
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